Charge Mode Readout (CMR) is one of the key building blocks of CMOS image sensor readout circuitry. They are used to perform correlated double sampling (CDS) in a CMOS image sensor by subtracting signal and reset voltages of CMOS active pixels. They can also be configured to convert single ended signal and reset voltages of a CMOS image sensor into a fully differential output signal by adding proper offset voltage to the signal and reset values.
The individual pixels in a selected CMOS image sensor pixel array row are simultaneously read out through individual columns readout circuitry to a line memory, where they are stored on sample-and-hold capacitors. Each pixel output comprises two signals: first, a “Sample” or photointegration signal which is proportional to the integrated photon flux captured by the photodiode during each integration period; and second, a “Reset” signal, which is a voltage level at which the pixel was held before the photon charge integration starts. Upon column readout, these stored signals are routed to a switched capacitor amplifier known as charge mode readout amplifier. The number of charge mode readout amplifiers required for reading out sampled pixel values is determined by the readout speed. The resulting voltage signal is input to an analog-to-digital converter (“ADC”) for conversion to a digital signal representing the differential between Sample signal and the Reset signal.
In typical CMR designs, signals from multiple columns are sequentially fed into a single readout channel. In this way, a single amplifier, ADC, and associated circuitry can serve multiple columns, making efficient use of power and area. However, high-performance amplifiers are usually required in CMR's due to their poor feedback factor and high speed requirements, which increases the image sensor readout power usage drastically. In fact, the CMR amplifiers have become one of the most power-hungry components in today's CMOS image sensors.
Accordingly, there is a need in the art for solutions, which will reduce the power consumed in reading out each column. Presented herein are novel circuits and associated methods that reduce power consumption while retaining the advantages of CMR readout. The invention encompasses the use of a shared amplifier for alternating stages readout that can process two channel's worth of columns, doubling the number of columns served by a single amplifier and significantly reducing the power utilized in reading out each column.